Reducing Power Consumption During Online and Offline Testing

Dedicated to my beloved family v Acknowledgments I would like to thank my advisor Prof. Nur A. Touba for his continuous support and guidance during the course of my PhD. I have always admired his clarity of thought and command over the subject and understanding. The high standards he sets for research are an inspiration for me. I would like to thank Prof. Margarida MacDonald for agreeing to be on my PhD committee and for reviewing my dissertation. I could not have done my PhD without the loving support and help of my husband Sugato Basu. Not only was he a great collaborator to work with, he gave me mental support during the difficult times. His confidence in me helped me believe in myself and I would like to thank him for being there for me always. I would like to thank all my friends at Austin for making my stay in Austin a memorable one. I would especially like to thank Sandip Ray for the long discussions that we had and for giving me the love of a brother. I would like to thank my parents-in-law Samir Basu and Nandita Basu and all my other relatives for their support. Last but not the least, I would like to thank my father Ashok Ghosh, my mother Rajyasri Ghosh and my brother Rajiv Ghosh for their unflinching love and support. They helped me at each and every step in realizing my dream and it is to them that I dedicate this dissertation. My parents' lives are a true source of inspiration for me and I am what I am because of them. This dissertation proposes techniques for power reduction in online and offline circuit testing. Power management is critical in both these domains, since high power dissipation can drive up production cost and even cause errors. The first part of the dissertation focuses on power reduction for online testing with concurrent error detection capabilities, where errors in the operation of the circuit are detected (and possibly corrected) at normal operational run-time. In online testing, power dissipation has lately become a first-order design criterion due to the significant hardware overhead for detecting/correcting errors and ensuring system reliability. Two problems are addressed, namely reducing power in concurrent error detection for (1) error correcting codes for memory checker, and (2) synthesis of parity prediction circuits. vii The next part of the dissertation discusses power …